Computing Architecture

The 1-Million-Bit Computer That Turns Noise Into an Advantage

Engineers at UC Santa Barbara have built the largest probabilistic computer to date — a programmable machine of 1 million "p-bits" that leans into randomness instead of fighting it.

• One million probabilistic bits (p-bits) spread across 18 networked FPGAs — roughly 140 times bigger than the previous record of 7,200 p-bits.
• The whole machine performs more than a trillion bit-flips per second, and it reaches that speed without global lockstep synchronization between its chips.
• It is a general-purpose, programmable device, not a single-purpose optimization chip — a distinction that sets it apart from QUBO solvers and Ising machines.

In an ordinary computer a bit is supposed to be stubborn. It stays a 0 or a 1, and if it flips on its own that is called noise — a defect to be engineered away. A probabilistic bit, or p-bit, does the exact opposite. It flips between 0 and 1 with a tunable probability, constantly churning. Individually a single p-bit looks useless, but many of them operating together in a correlated pattern behave like a giant probability distribution that can be shaped to find solutions to problems defined by chance.

The class of problems these machines target is called stochastic optimization — finding the best configuration among many possibilities, such as the shortest delivery route through dozens of stops, the most efficient way to schedule power across a grid, or the best allocation of limited resources. These are the same kinds of problems quantum computers are often promoted for, but a probabilistic computer does not need near-zero temperatures, vacuum chambers, or qubits that collapse when touched. It runs on ordinary, reconfigurable silicon — field-programmable gate arrays, or FPGAs — at room temperature.

The jump from 7,200 p-bits on a single chip to 1 million p-bits spread across 18 networked chips was the real engineering hurdle. Because the machine works through correlated fluctuations, you cannot just wire FPGAs together the way you wire CPUs or GPUs; the chips have to stay in step with each other's randomness. The team, led by Kerem Çamsarı at UC Santa Barbara with lead author Navid Anjum Aadit at Stanford, discovered a simple, predictable design rule governing how quickly the chips must exchange data to behave as one machine. Below that communication threshold the computer faces a straightforward trade-off between speed and accuracy, but above it the distributed array acts as a single coherent solver.

What makes the result conceptually interesting is not just the scale but the philosophy behind it. Conventional computing treats randomness as an enemy and spends enormous effort suppressing it. A probabilistic computer inverts that: noise becomes the raw material of computation, and the hardware is designed to orchestrate rather than erase it. The researchers note that the machine is programmable and general-purpose, so it is not a dedicated accelerator for one niche task but a different kind of CPU-like engine for a different class of problems.

The honest caveat is that the device is a research machine, not a product. Probabilistic computing is most competitive on a specific slice of optimization problems, and whether p-bit hardware can outperform tuned classical algorithms and specialized chips on real-world workloads is still an open question. But the demonstration shows that the scaling barrier many assumed would block the technology — wiring many noisy chips into one synchronized machine — can be crossed with a clean design rule, opening the path toward even larger arrays.